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<title>Sample Waveforms for "FIFO.v" </title>
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<h2><CENTER>Sample behavioral waveforms for design file "FIFO.v" </CENTER></h2>
<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "FIFO.v".  The design "FIFO.v" has a depth of 2048 words of 128 bits each. The fifo is in show-ahead synchronous mode.  The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
<CENTER><img src=FIFO_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
<CENTER><img src=FIFO_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design for FIFO full condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
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